1. Technical Field
The embodiments herein generally relate to wireless technologies, and, more particularly, to Digital Video Broadcasting over Handled (DVB-H) technologies.
2. Description of the Related Art
A DVB-H device transmitter uses a Reed-Solomon (RS) encoder along with an interleaver to provide protection from burst errors caused by impairments in the communication channel. In DVB-H receivers, a RS decoder and deinterleaver are generally required to recover the transmitted data. This deinterleaver requires storage of an entire “frame” of data, and typically the most efficient way to implement this is data storage with a Random Access Memory (RAM) which is referred to as the Multi-Protocol Encapsulator Forward Error Correction (MPE-FEC) RAM. However, due to the large amount of data in the MPE-FEC RAM, the implementation of this RAM has a significant impact on the silicon area and power consumption of the DVB-H receiver.
The function of the MPE-FEC RAM is as follows:
1. Internet Protocol (IP) datagrams are written into the RAM column-by-column by the Transport-stream packet de-multiplexer (TS demux).
2. IP datagrams are read from the RAM row-by-row for input to the RS decoder.
3. The RS decoder output is written to the RAM row-by-row.
4. The corrected IP datagrams are read from the RAM column-by-column for post-processing and output.
Accordingly, it can been seen there are multiple interfaces that require access to the RAM simultaneously; however, the RAM can only have a single access port because additional ports would make the RAM prohibitively large. The first challenge is to find an architecture which uses a single-port MPE-FEC RAM.
The second challenge is to implement this RAM with low power consumption. The sheer size of the RAM (a minimum of 255 k bytes of storage is required for one DVB-H frame) leads to a large RAM which consumes significant power.
The third challenge is to find an addressing scheme for this RAM which can handle the reception of multiple back-to-back frames of data; i.e., the RAM has to store the second frame without overwriting the previous frame.
Conventionally, the DVB-H receiver MPE-FEC memory is implemented off-chip. Compared to an on-chip RAM, the off-chip RAM generally requires: 1) more power consumption due to switching of signals on the circuit board between the DVB-H demodulator chip and the MPE-FEC RAM chip; 2) more circuit board area because the overall solution requires two chips rather than one; and 3) more overall processing cost because of additional silicon, packaging, and testing costs for the separate memory chip. Therefore, there remains a need for a new MPE-FEC RAM for DVB-H receivers.